Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer logic (RTL) representation of the functional circuit design, synthesize a “netlist” from the RTL representation, and implement a layout from the netlists. Synthesis of the netlist and implementation of the layout involve simulating the operation of the circuit and determining where cells should be placed and where the interconnects that couple the cells together should be routed. Timing signoff is one of the last steps in the IC design process and ensures that signal propagation speed in a newly-designed circuit is such that the circuit will operate as intended. Even with EDA tools designed to coordinate the timing in integrated circuits, current design methodologies are limited at the point of clock-tree-synthesis (CTS).
Typical design methodologies for integrated circuits with multiple clock domains require the design team provide estimates of clock insertion delays based on designer knowledge. Given the complexity of inter-clock transfers in modern designs and the sheer number of clock domains, it is usually not possible for the design team to understand all the inter-clock transfers that can be impacted by the clock-tree insertion delays. One way to get an interface between clock domains to operate properly is to align the insertion delay of the two clock-trees at the top level of design flow for the integrated circuit. Thus, clock signals can be externally aligned before being provided to different modules of the integrated circuit. This, however, can be difficult because the clock-trees usually have different loading. Additionally, on-chip-variation (OCV), crosstalk and other effects make this clock alignment more challenging with new technologies. Accordingly, problems with the design of the integrated circuit can occur.